aschnell

aschnell

HelenOS: <filesystem> of a down

a project by jjindrak

During the previous Hackweek [0], I have successfully implemented, tested and merged [1] an implementation of the entire C++ standard header <future>. This time, my aim is to modernize the C++14-esque standard library [2] of HelenOS [3][4] with a C++17 feature - the <filesystem> header. The <filesystem> header is much larger than the <future> header which I barely managed to implement and test in the allocated time for the previous Hackweek, but <future> was mostly OS-independent as it relied only on previously implemented features of the standard library. The <filesystem> header, however, is limited by the filesystem API of the OS and as such implementing of the entirety of it might not be possible, limiting the scope of the project (which is a good thing due to the time constraints). The primary features of the header [5] that should be implemented:

Updated about 3 years ago. No love. 1 follower.

Port some classic game to Linux

a project by MDoucha

Let's pick some old classic game, reverse engineer the data formats and game rules and write an open source engine for it from scratch. Some games from 1990s are simple enough that we could have a playable prototype by the end of the week. Write which games you'd like to hack on in the comments. Don't forget to check e.g. on Open Source Game Clones, Github and SourceForge whether the game is ported already.

Updated 6 months ago. 31 hacker ♥️. 17 followers.

SMTGCC

a project by fkastl

Project Description

There's a project experimenting with verifying GCC optimizations using SMT solvers. Currently there is only one person working on this project. Analyzing compilers with SMT solvers seems like a cool new topic to me. Let's see how we could help.

Updated 6 months ago. 2 hacker ♥️. 2 followers.

Tungsten: A low-level LLVM programming language

a project by mfriedrich

Project Description

> Tungsten is supposed to be a memory-safe and type-safe language front-end for LLVM which borrows many elements from C and C# syntax.

Updated 6 months ago. No love. 2 followers.

Avahi Integration and Network Connection

a project by vojha

Avahi Integration and Network Connection

Project Description

Updated 5 months ago. 2 hacker ♥️. 1 follower.

Saline (state deployment control and monitoring tool for SUSE Manager/Uyuni)

a project by vizhestkov

Project Description

Saline is an addition for salt used in SUSE Manager/Uyuni aimed to provide better control and visibility for states deploymend in the large scale environments.

Updated 6 months ago. 6 hacker ♥️. 1 follower.

Grab precise changes in log file/s between system events

a project by smhalas

Project Description

The goal of this project is to create a tool to monitor changes in a log file or any text file between specific events in the system.

Updated 6 months ago. 1 hackers ♥️. 1 follower.
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Activity

  • 6 months ago: aschnell started AVR UART and Bootloader
  • 6 months ago: aschnell liked AVR UART and Bootloader
  • 6 months ago: aschnell originated AVR UART and Bootloader
  • over 1 year ago: aschnell started Create RISC-V Core using VHDL suitable for TinyFPGA BX
  • over 1 year ago: aschnell liked Create RISC-V Core using VHDL suitable for TinyFPGA BX
  • over 1 year ago: aschnell originated Create RISC-V Core using VHDL suitable for TinyFPGA BX
  • over 1 year ago: aschnell liked Humidity sensors with dashboard
  • about 3 years ago: aschnell added keyword "software-definded-hardware" to Program FPGA using Verilog and VHDL
  • about 3 years ago: aschnell removed keyword software-definedhardware from Program FPGA using Verilog and VHDL
  • about 3 years ago: aschnell added keyword "software-definedhardware" to Program FPGA using Verilog and VHDL
  • about 3 years ago: aschnell added keyword "fpga" to Program FPGA using Verilog and VHDL
  • about 3 years ago: aschnell added keyword "verilog" to Program FPGA using Verilog and VHDL
  • about 3 years ago: aschnell added keyword "vhdl" to Program FPGA using Verilog and VHDL
  • about 3 years ago: aschnell started Program FPGA using Verilog and VHDL
  • about 3 years ago: aschnell liked Program FPGA using Verilog and VHDL
  • about 3 years ago: aschnell originated Program FPGA using Verilog and VHDL
  • almost 5 years ago: aschnell started Custom Style for Devicegraph Output of libstorage-ng
  • almost 5 years ago: aschnell liked Custom Style for Devicegraph Output of libstorage-ng
  • almost 5 years ago: aschnell originated Custom Style for Devicegraph Output of libstorage-ng
  • almost 5 years ago: aschnell started Look at New Parallelisation Technologies
  • almost 5 years ago: aschnell liked Look at New Parallelisation Technologies
  • almost 5 years ago: aschnell originated Look at New Parallelisation Technologies
  • almost 6 years ago: aschnell started add features to libstorage-ng
  • almost 6 years ago: aschnell liked add features to libstorage-ng
  • almost 6 years ago: aschnell originated add features to libstorage-ng
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