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8 months ago: aschnell liked Understand and maybe implement optimal solution finder for Rubik's Cube using IDA* algorithm
8 months ago: aschnell added keyword "ida*" to Understand and maybe implement optimal solution finder for Rubik's Cube using IDA* algorithm
8 months ago: aschnell added keyword "puzzle" to Understand and maybe implement optimal solution finder for Rubik's Cube using IDA* algorithm
8 months ago: aschnell added keyword "rubik" to Understand and maybe implement optimal solution finder for Rubik's Cube using IDA* algorithm
8 months ago: aschnell started Understand and maybe implement optimal solution finder for Rubik's Cube using IDA* algorithm
8 months ago: aschnell originated Understand and maybe implement optimal solution finder for Rubik's Cube using IDA* algorithm
over 1 year ago: aschnell started AVR UART and Bootloader
over 1 year ago: aschnell liked AVR UART and Bootloader
over 1 year ago: aschnell originated AVR UART and Bootloader
over 2 years ago: aschnell started Create RISC-V Core using VHDL suitable for TinyFPGA BX
over 2 years ago: aschnell liked Create RISC-V Core using VHDL suitable for TinyFPGA BX
over 2 years ago: aschnell originated Create RISC-V Core using VHDL suitable for TinyFPGA BX
over 2 years ago: aschnell liked Humidity sensors with dashboard
over 4 years ago: aschnell added keyword "software-definded-hardware" to Program FPGA using Verilog and VHDL
over 4 years ago: aschnell removed keyword software-definedhardware from Program FPGA using Verilog and VHDL
over 4 years ago: aschnell added keyword "software-definedhardware" to Program FPGA using Verilog and VHDL
over 4 years ago: aschnell added keyword "fpga" to Program FPGA using Verilog and VHDL
over 4 years ago: aschnell added keyword "verilog" to Program FPGA using Verilog and VHDL
over 4 years ago: aschnell added keyword "vhdl" to Program FPGA using Verilog and VHDL
over 4 years ago: aschnell started Program FPGA using Verilog and VHDL
over 4 years ago: aschnell liked Program FPGA using Verilog and VHDL
over 4 years ago: aschnell originated Program FPGA using Verilog and VHDL
about 6 years ago: aschnell started Custom Style for Devicegraph Output of libstorage-ng
about 6 years ago: aschnell liked Custom Style for Devicegraph Output of libstorage-ng
about 6 years ago: aschnell originated Custom Style for Devicegraph Output of libstorage-ng
