Create a single-cycle 32-bit RISC-V Core in VHDL as a pure learning project. Why RISC-V? It is clean and small (the base has only about 40 instructions) and has a lot of momentum. Also openSUSE provides a complete tool-chain. Why TinyFPGA BX? A full set of open source tools is available for the iCE40 FPGA (first FPGA where the bitstream was reverse engineered).
The goal is to run a simple program (likely just flashing a few LEDs) written in C on real hardware.
Looking for hackers with the skills:
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This project is part of:
Hack Week 22
This project is one of its kind!