Description

There are multiple ways to run RISC-V software on other architectures like x86. The most common options are to use QEMU in either userspace emulation mode (only specific processes are emulated, syscalls are passed through to the host kernel) or system emulation mode (full kernel- and userspace are emulated, with virtual devices).

Full system emulation is rather slow, as it has to spend time emulating devices and the MMU for all memory access.

Userspace emulation usually has less overhead, but there are some downsides: Sometimes kernel emulation is necessary or QEMU is lacking some syscalls needed by programs (like some tty ioctls currently, which leads to a missing shell prompt with recent glibc).

The idea of this project is to write a full system emulator with minimal overhead, by passing through physical (resp. QEMU virtual) hardware as much as possible. Running in kernel mode makes it possible to use the x86 MMU to perform translations set up by the emulated RISC-V system. Some types of devices (PCI, other kinds of MMIO, ...) may be passed through directly, others have to be emulated to some extent (interrupt cotrollers, timers, serial, ...).

The emulator will be started as an EFI executable, which then loads the RISC-V kernel, initrd and starts emulation, at which point it appears from the outside as if it was running natively.

Goals

The emulator should be able to run inside an qemu-system-x86_64 -accel kvm instance and boot mainline linux (Tumbleweed?) successfully. As a PoC, the first stage of development may use an interpreted CPU implementation only and only support a single hart.

Steps after that are: getting it to run on real HW, SMP (multi-core), simple JIT, optimizing JIT (maybe LLVM based?). Running some riscv64 builds with osc using this would be interesting to compare behaviour and performance.

Resources

Last year's project, a slow RV32 system emulator in GLSL
RISC-V ISA Specifications