Create a single-cycle 32-bit RISC-V Core in VHDL as a pure learning project. Why RISC-V? It is clean and small (the base has only about 40 instructions) and has a lot of momentum. Also openSUSE provides a complete tool-chain. Why TinyFPGA BX? A full set of open source tools is available for the iCE40 FPGA (first FPGA where the bitstream was reverse engineered).

The goal is to run a simple program (likely just flashing a few LEDs) written in C on real hardware.

Looking for hackers with the skills:

Nothing? Add some keywords!

This project is part of:

Hack Week 22

Activity

  • about 1 year ago: clin liked this project.
  • about 1 year ago: pvorel liked this project.
  • about 1 year ago: iivanov liked this project.
  • about 1 year ago: sushilhiremath liked this project.
  • about 1 year ago: sushilhiremath joined this project.
  • about 1 year ago: dmdiss liked this project.
  • about 1 year ago: mbrugger liked this project.
  • about 1 year ago: aschnell started this project.
  • about 1 year ago: aschnell liked this project.
  • about 1 year ago: aschnell originated this project.

  • Comments

    • sushilhiremath
      about 1 year ago by sushilhiremath | Reply

      Hi Arvin Schnell, I would like to contribute this project with my limited knowledge in RISC architecture and to mentione about my experience in FPGA/VHDL programming, i have done it during my masters thesis submission(it was way back 10 year ago i have lost touch with FPGA). I am comfortable in C and Kernel programming.

    • aschnell
      about 1 year ago by aschnell | Reply

      I have created the repository https://github.com/aschnell/riscv-cpu.

    • aschnell
      about 1 year ago by aschnell | Reply

      Result: The RISC-V CPU works fine and can run very simple C programs. One problem is that it does not use the Block RAM of the FPGA. That makes it use lots of logic cells and apparently also slows it down. To use Block RAM the RAM must be synchronous for read and write. Doing so would turn the architecture from single-cycle to multi-cycle and thus is not possible in the remaining time. But apart from that the CPU works fine and it was one of the most interesting hackweek projects I have ever worked on.

    Similar Projects

    This project is one of its kind!