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  almost 2 years ago by sushilhiremath | Reply

  Hi Arvin Schnell, I would like to contribute this project with my limited knowledge in RISC architecture and to mentione about my experience in FPGA/VHDL programming, i have done it during my masters thesis submission(it was way back 10 year ago i have lost touch with FPGA). I am comfortable in C and Kernel programming.

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Hi Arvin Schnell, I would like to contribute this project with my limited knowledge in RISC architecture and to mentione about my experience in FPGA/VHDL programming, i have done it during my masters thesis submission(it was way back 10 year ago i have lost touch with FPGA). I am comfortable in C and Kernel programming.
 
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Reply to sushilhiremath
Hi Arvin Schnell, I would like to contribute this project with my limited knowledge in RISC architecture and to mentione about my experience in FPGA/VHDL programming, i have done it during my masters thesis submission(it was way back 10 year ago i have lost touch with FPGA). I am comfortable in C and Kernel programming.
---
# A First Level Header
## A Second Level Header

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This is an [link to example.com](http://example.com/)

This is an image ![an openSUSE geeko icon](https://en.opensuse.org/images/d/d0/Icon-distribution.png)

This is a user link @hans

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  almost 2 years ago by aschnell | Reply

  I have created the repository https://github.com/aschnell/riscv-cpu.

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I have created the repository https://github.com/aschnell/riscv-cpu.
 
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I have created the repository https://github.com/aschnell/riscv-cpu.
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# A First Level Header
## A Second Level Header

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  almost 2 years ago by aschnell | Reply

  Result: The RISC-V CPU works fine and can run very simple C programs. One problem is that it does not use the Block RAM of the FPGA. That makes it use lots of logic cells and apparently also slows it down. To use Block RAM the RAM must be synchronous for read and write. Doing so would turn the architecture from single-cycle to multi-cycle and thus is not possible in the remaining time. But apart from that the CPU works fine and it was one of the most interesting hackweek projects I have ever worked on.

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Edit Comment 7022
# A First Level Header
## A Second Level Header

Use one asterisk to *emphasize*

Use two asterisks for **strong emphasis**

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This is an [link to example.com](http://example.com/)

This is an image ![an openSUSE geeko icon](https://en.opensuse.org/images/d/d0/Icon-distribution.png)

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Result: The RISC-V CPU works fine and can run very simple C programs. One problem is that it does not use the Block RAM of the FPGA. That makes it use lots of logic cells and apparently also slows it down. To use Block RAM the RAM must be synchronous for read and write. Doing so would turn the architecture from single-cycle to multi-cycle and thus is not possible in the remaining time. But apart from that the CPU works fine and it was one of the most interesting hackweek projects I have ever worked on.
 
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Reply to aschnell
Result: The RISC-V CPU works fine and can run very simple C programs. One problem is that it does not use the Block RAM of the FPGA. That makes it use lots of logic cells and apparently also slows it down. To use Block RAM the RAM must be synchronous for read and write. Doing so would turn the architecture from single-cycle to multi-cycle and thus is not possible in the remaining time. But apart from that the CPU works fine and it was one of the most interesting hackweek projects I have ever worked on.
---
# A First Level Header
## A Second Level Header

Use one asterisk to *emphasize*

Use two asterisks for **strong emphasis**

- Use hyphens
- for unordereed
- lists

This is an [link to example.com](http://example.com/)

This is an image ![an openSUSE geeko icon](https://en.opensuse.org/images/d/d0/Icon-distribution.png)

This is a user link @hans

This is a project link hw#some-cool-title
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