Projects in the topic risc-v

RISC-V boot deep dive (Boot FLOW from 0 to Linux Kernel) a project by clin RISC-V boot deep dive (Boot FLOW from 0 to Linux Kernel) Make RISC-V boot like rest of industry U-boot for embedded, UEFI for consumer and servers Updated over 3 years ago. 2 hacker ♥️. 5 followers.
Create openSUSE images for Arm/RISC-V boards an invention by avicenzi Project Description Create openSUSE images (or test generic EFI images) for Arm and/or RISC-V boards that are not yet supported. Updated 21 days ago. 4 hacker ♥️. 2 followers.
Tumbleweed on Mars-CM (RISC-V board) a project by ph03nix RISC-V is awesome, Tumbleweed is awesome, chocolate cake is awesome. I'm planning to combine all of them in one project. Project Description Updated 11 months ago. 2 hacker ♥️. 1 follower.
RISC-V CPU on FPGA an invention by mkoutny Project Description Software engineers should be proficient in their area of expertise and also have overview of adjacent abstraction layers to understand the world in better context. Despite SUSE is not a hardware company, this project aims at implementing a simple RISC-V processor on a hobby FPGA board. Updated 10 months ago. No love. 2 followers.
FizzBuzz OS a project by mssola Project Description FizzBuzz OS (or just `fbos`) is an idea I've had in order to better grasp the fundamentals of the low level of a RISC-V machine. In practice, I'd like to build a small Operating System kernel that is able to launch three processes: one that simply prints "Fizz", another that prints "Buzz", and the third which prints "FizzBuzz". These processes are unaware of each other and it's up to the kernel to schedule them by using the timer interrupts as given on openSBI (fizz on % 3 seconds, buzz on % 5 seconds, and fizzbuzz on % 15 seconds). Updated 20 days ago. No love. 1 follower.

RISC-V boot deep dive (Boot FLOW from 0 to Linux Kernel)

a project by clin

RISC-V boot deep dive (Boot FLOW from 0 to Linux Kernel)

Make RISC-V boot like rest of industry U-boot for embedded, UEFI for consumer and servers

Updated over 3 years ago. 2 hacker ♥️. 5 followers.

Create openSUSE images for Arm/RISC-V boards

an invention by avicenzi

Project Description

Create openSUSE images (or test generic EFI images) for Arm and/or RISC-V boards that are not yet supported.

Updated 21 days ago. 4 hacker ♥️. 2 followers.

Tumbleweed on Mars-CM (RISC-V board)

a project by ph03nix

RISC-V is awesome, Tumbleweed is awesome, chocolate cake is awesome. I'm planning to combine all of them in one project.

Project Description

Updated 11 months ago. 2 hacker ♥️. 1 follower.

RISC-V CPU on FPGA

an invention by mkoutny

Project Description

Software engineers should be proficient in their area of expertise and also have overview of adjacent abstraction layers to understand the world in better context. Despite SUSE is not a hardware company, this project aims at implementing a simple RISC-V processor on a hobby FPGA board.

Updated 10 months ago. No love. 2 followers.

FizzBuzz OS

a project by mssola

Project Description

FizzBuzz OS (or just fbos) is an idea I've had in order to better grasp the fundamentals of the low level of a RISC-V machine. In practice, I'd like to build a small Operating System kernel that is able to launch three processes: one that simply prints "Fizz", another that prints "Buzz", and the third which prints "FizzBuzz". These processes are unaware of each other and it's up to the kernel to schedule them by using the timer interrupts as given on openSBI (fizz on % 3 seconds, buzz on % 5 seconds, and fizzbuzz on % 15 seconds).

Updated 20 days ago. No love. 1 follower.