RISC-V CPU on FPGA
an invention by mkoutny
Updated almost 2 years ago. No love. 2 followers.

Project Description

Software engineers should be proficient in their area of expertise and also have overview of adjacent abstraction layers to understand the world in better context. Despite SUSE is not a hardware company, this project aims at implementing a simple RISC-V processor on a hobby FPGA board.

More details are in project repo's README.

Goal for this Hackweek

  • Get familiar with FPGA tools
  • Peek into HDL (hardware definition languages)
  • Design the CPU using SystemVerilog
  • Create a demo program to run on the CPU
  • Run the circuit in a simulator and eventually on the FPGA too
  • Implement some non-trivial features like pipelining or some instruction set extension

Resources

Looking for hackers with the skills:

risc-v fpga clang verilog

This project is part of:

Hack Week 23

Activity

  • almost 2 years ago: PPavlu joined this project.
  • almost 2 years ago: mkoutny added keyword "risc-v" to this project.
  • almost 2 years ago: mkoutny added keyword "fpga" to this project.
  • almost 2 years ago: mkoutny added keyword "clang" to this project.
  • almost 2 years ago: mkoutny added keyword "verilog" to this project.
  • almost 2 years ago: mkoutny started this project.
  • almost 2 years ago: mkoutny originated this project.


    • Comments

    • mkoutny
      almost 2 years ago by mkoutny | Reply

      We implemented several blocks of the circuitry:

      • control (roughly fetch/decode),
      • register file,
      • ALU,
      • block RAM,
      • memory control (for unaligned access).

      We also implemented memory mapped IO (using serial over USB block provided by TinyFPGA's library).

      Additionally, we made a simple demo program and tooling to cross-compile it on non-RISC-V machine and prepare it to "load" it to FPGA board's memory.

      Every circuit block is accompanied with (simulator) testsuite and they pass \o/ We didn't manage to run the circuit on FPGA, probably because of memory data preloading or cumbersome IO. That will need more debugging in the future. (Hence we also didn't get down to any of the non-trivial features.)

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